? semiconductor components industries, llc, 2012 july, 2012 ? rev. 7 1 publication order number: mc74lcx125/d mc74lcx125 low-voltage cmos quad buffer with 5 v ? tolerant inputs and outputs (3 ? state, non ? inverting) the mc74lcx125 is a high performance, non ? inverting quad buffer operating from a 2.3 to 3.6 v supply. high impedance ttl compatible inputs significantly reduce current loading to input drivers while ttl compatible outputs offer improved switching noise performance. a v i specification of 5.5 v allows mc74lcx125 inputs to be safely driven from 5.0 v devices. the mc74lcx125 is suitable for memory address driving and all ttl level bus oriented transceiver applications. current drive capability is 24 ma at the outputs. the output enable (oe n) inputs, when high, disable the outputs by placing them in a high z condition. features ? designed for 2.3 to 3.6 v v cc operation ? 5.0 v tolerant ? interface capability with 5.0 v ttl logic ? supports live insertion and withdrawal ? i off specification guarantees high impedance when v cc = 0 v ? lvttl compatible ? lvcmos compatible ? 24 ma balanced output sink and source capability ? near zero static supply current in all three logic states (10 a) substantially reduces system power requirements ? latchup performance exceeds 500 ma ? esd performance: human body model >2000 v machine model >200 v ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant marking diagrams tssop ? 14 dt suffix case 948g 14 1 soic ? 14 d suffix case 751a 14 1 see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information http://onsemi.com lcx125g awlyww 1 14 lcx 125 alyw 1 14 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package (note: microdot may be in either location)
mc74lcx125 http://onsemi.com 2 figure 1. pinout: 14 ? lead (top view) 13 14 12 11 10 9 8 2 1 34567 v cc oe 3d3 o3oe 2d2 o2 oe 0d0 o0oe 1 d1 o1 gnd pin names function output enable inputs data inputs 3 ? state outputs pins oe n dn on h = high voltage level l = low voltage level z = high impedance state x = high or low v oltage level and transitions are acceptable; for i cc reasons, do not float inputs oe n dn on l l h l h x l h z inputs outputs truth table d0 2 o0 3 oe 0 1 d1 5 o1 6 oe 1 4 d2 9 o2 8 oe 2 10 d3 12 o3 11 oe 3 13 figure 2. logic diagram maximum ratings symbol parameter value condition units v cc dc supply voltage ? 0.5 to +7.0 v v i dc input voltage ? 0.5 v i +7.0 v v o dc output voltage ? 0.5 v o +7.0 output in 3 ? state v ? 0.5 v o v cc + 0.5 output in high or low state. (note 1) v i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma +50 v o > v cc ma i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range ? 65 to +150 c msl moisture sensitivity level 1 maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed.
mc74lcx125 http://onsemi.com 3 recommended operating conditions symbol parameter min typ max units v cc supply voltage operating data retention only 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 v v i input voltage 0 5.5 v v o output voltage high or low state 3 ? state 0 0 v cc 5.5 v i oh high level output current v cc = 3.0 v ? 3.6 v v cc = 2.7 v ? 3.0 v v cc = 2.3 v ? 2.7 v ? 24 ? 12 ? 8 ma i ol low level output current v cc = 3.0 v ? 3.6 v v cc = 2.7 v ? 3.0 v v cc = 2.3 v ? 2.7 v +24 +12 +8 ma t a operating free ? air temperature ? 40 +85 c t/ v input transition rise or fall rate, v in from 0.8 v to 2.0 v, v cc = 3.0 v 0 10 ns/v dc electrical characteristics t a = ? 40 c to +85 c symbol characteristic condition min max units v ih high level input voltage (note 2) 2.3 v v cc 2.7 v 1.7 v 2.7 v v cc 3.6 v 2.0 v il low level input voltage (note 2) 2.3 v v cc 2.7 v 0.7 v 2.7 v v cc 3.6 v 0.8 v oh high level output voltage 2.3 v v cc 3.6 v; i ol = 100 a v cc ? 0.2 v v cc = 2.3 v; i oh = ? 8 ma 1.8 v cc = 2.7 v; i oh = ? 12 ma 2.2 v cc = 3.0 v; i oh = ? 18 ma 2.4 v cc = 3.0 v; i oh = ? 24 ma 2.2 v ol low level output voltage 2.3 v v cc 3.6 v; i ol = 100 a 0.2 v v cc = 2.3 v; i ol = 8 ma 0.6 v cc = 2.7 v; i ol = 12 ma 0.4 v cc = 3.0 v; i ol = 16 ma 0.4 v cc = 3.0 v; i ol = 24 ma 0.55 i oz 3 ? state output current v cc = 3.6 v, v in = v ih or v il , v out = 0 to 3.6 v 5 a i off power off leakage current v cc = 0, v in = 3.6 v or v out = 3.6 v 10 a i in input leakage current v cc = 0 to 3.6 v, v in = 3.6 v or gnd 5 a i cc quiescent supply current v cc = 3.6 v, v in = 3.6 v or v out = 3.6 v 10 a i cc increase in i cc per input 2.3 v cc 3.6 v; v ih = v cc ? 0.6 v 500 a 2. these values of v i are used to test dc electrical characteristics only.
mc74lcx125 http://onsemi.com 4 ac characteristics t r = t f = 2.5 ns; r l = 500 symbol parameter waveform limits units t a = ? 40 c to +85 c v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 2.5 v 0.2 v c l = 50 pf c l = 50 pf c l = 30 pf min max min max min max t plh t phl propagation delay time input to output 1 1.5 1.5 6.0 6.0 1.5 1.5 6.5 6.5 1.5 1.5 7.2 7.2 ns t pzh t pzl output enable time to high and low level 2 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 1.5 1.5 9.1 9.1 ns t phz t plz output disable time from high and low level 2 1.5 1.5 6.0 6.0 1.5 1.5 7.0 7.0 1.5 1.5 7.2 7.2 ns t oshl t oslh output ? to ? output skew (note 3) 1.0 1.0 ns 3. skew is defined as the absolute value of the dif ference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either high ? to ? low (t oshl ) or low ? to ? high (t oslh ); parameter guaranteed by design. dynamic switching characteristics t a = +25 c symbol characteristic condition min typ max units v olp dynamic low peak voltage (note 4) v cc = 3.3 v, c l = 50 pf, v ih = 3.3 v, v il = 0 v v cc = 2.5 v, c l = 30 pf, v ih = 2.5 v, v il = 0 v 0.8 0.6 v v olv dynamic low valley voltage (note 4) v cc = 3.3 v, c l = 50 pf, v ih = 3.3 v, v il = 0 v v cc = 2.5 v, c l = 30 pf, v ih = 2.5 v, v il = 0 v ? 0.8 ? 0.6 v 4. number of outputs defined as ?n?. measured with ?n ? 1? outputs switching from high ? to ? low or low ? to ? high. the remaining output is measured in the low state. capacitive characteristics symbol parameter condition typical units c in input capacitance v cc = 3.3 v, v i = 0 v or v cc 7 pf c out output capacitance v cc = 3.3 v, v i = 0 v or v cc 8 pf c pd power dissipation capacitance 10 mhz, v cc = 3.3 v, v i = 0 v or v cc 25 pf ordering information device package shipping ? mc74lcx125dg soic ? 14 (pb ? free) 55 units / rail mc74lcx125dr2g soic ? 14 (pb ? free) 2500 tape & reel mc74lcx125dtg tssop ? 14 (pb ? free) 96 units / rail mc74lcx125dtr2g tssop ? 14 (pb ? free) 2500 tape & reel NLVLCX125DTR2G tssop ? 14* (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified.
mc74lcx125 http://onsemi.com 5 waveform 1 ? propagation delays t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v v oh v ol dn on t phl t plh waveform 2 ? output enable and disable times t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v 0 v oe n on t pzh 3.0 v t phz t pzl t plz on vmi vmi vmo vmo figure 3. ac waveforms v cc v oh ? 0.3 v v ol + 0.3 v gnd symbol v cc 3.3 v 0.3 v 2.7 v 2.5 v 0.2 v vmi 1.5 v 1.5 v v cc /2 vmo 1.5 v 1.5 v v cc /2 vmi vmi vmo vmo pulse generator r t dut v cc r l c l c l = 50 pf at v cc = 3.3 0.3 v or equivalent (includes jig and probe capacitance) c l = 30 pf at v cc = 2.5 0.2 v or equivalent (includes jig and probe capacitance) r l = r 1 = 500 or equivalent r t = z out of pulse generator (typically 50 ) figure 4. test circuit
mc74lcx125 http://onsemi.com 6 package dimensions soic ? 14 nb case 751a ? 03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74lcx125 http://onsemi.com 7 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc74lcx125/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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